technical data 432 8-bit serial or parallel-input/ serial-output shift register with input latch high-performance silicon-gate cmos the in74hc597 is identical in pinout to the ls/als597. the device inputs are compatible with standard cmos outputs; with pullup resistors, they are compatible with ls/alsttl outputs. this device consists of an 8-bit input latch which feeds parallel data to an 8-bit shift register. data can also be loaded serially (see function table). ? outputs directly interface to cmos, nmos, and ttl ? operating voltage range: 2.0 to 6.0 v ? low input current: 1.0 a ? high noise immunity characteristic of cmos devices in74hc597 ordering information IN74HC597N plastic in74hc597d soic t a = -55 to 125 c for all packages pin assignment logic diagram pin 16 =v cc pin 8 = gnd
in74hc597 433 maximum ratings * symbol parameter value unit v cc dc supply voltage (referenced to gnd) -0.5 to +7.0 v v in dc input voltage (referenced to gnd) -1.5 to v cc +1.5 v v out dc output voltage (referenced to gnd) -0.5 to v cc +0.5 v i in dc input current, per pin 20 ma i out dc output current, per pin 25 ma i cc dc supply current, v cc and gnd pins 50 ma p d power dissipation in still air, plastic dip+ soic package+ 750 500 mw tstg storage temperature -65 to +150 c t l lead temperature, 1 mm from case for 10 seconds (plastic dip or soic package) 260 c * maximum ratings are those values beyond which damage to the device may occur. functional operation should be restricted to the recommended operating conditions. +derating - plastic dip: - 10 mw/ c from 65 to 125 c soic package: : - 7 mw/ c from 65 to 125 c recommended operating conditions symbol parameter min max unit v cc dc supply voltage (referenced to gnd) 2.0 6.0 v v in , v out dc input voltage, output voltage (referenced to gnd) 0 v cc v t a operating temperature, all package types -55 +125 c t r , t f input rise and fall time (figure 1) v cc =2.0 v v cc =4.5 v v cc =6.0 v 0 0 0 1000 500 400 ns this device contains protection circuitry to guard against damage due to high static voltages or electric fields. however, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high-impedance circuit. for proper operation, v in and v out should be constrained to the range gnd (v in or v out ) v cc . unused inputs must always be tied to an appropriate logic voltage level (e.g., either gnd or v cc ). unused outputs must be left open.
in74hc597 434 dc electrical characteristics (voltages referenced to gnd) v cc guaranteed limit symbol parameter test conditions v 25 c to -55 c 85 c 125 c unit v ih minimum high-level input voltage v out =0.1 v or v cc -0.1 v ? i out ? 20 a 2.0 4.5 6.0 1.5 3.15 4.2 1.5 3.15 4.2 1.5 3.15 4.2 v v il maximum low - level input voltage v out =0.1 v or v cc -0.1 v ? i out ? 20 a 2.0 4.5 6.0 0.3 0.9 1.2 0.3 0.9 1.2 0.3 0.9 1.2 v v oh minimum high-level output voltage v in =v ih or v il ? i out ? 20 a 2.0 4.5 6.0 1.9 4.4 5.9 1.9 4.4 5.9 1.9 4.4 5.9 v v in =v ih or v il ? i out ? 4.0 ma ? i out ? 5.2 ma 4.5 6.0 3.98 5.48 3.84 5.34 3.7 5.2 v ol maximum low-level output voltage v in =v ih or v il ? i out ? 20 a 2.0 4.5 6.0 0.1 0.1 0.1 0.1 0.1 0.1 0.1 0.1 0.1 v v in =v ih or v il ? i out ? 4.0 ma ? i out ? 5.2 ma 4.5 6.0 0.26 0.26 0.33 0.33 0.4 0.4 i in maximum input leakage current v in =v cc or gnd 6.0 0.1 1.0 1.0 a i cc maximum quiescent supply current (per package) v in =v cc or gnd i out =0 a 6.0 8.0 80 160 a
in74hc597 435 ac electrical characteristics (c l =50pf,input t r =t f =6.0 ns) v cc guaranteed limit symbol parameter v 25 c to -55 c 85 c 125 c unit f max minimum clock frequency (50% duty cycle) (figures 2 and 8) 2.0 4.5 6.0 6.0 30 35 4.8 24 28 4.0 20 24 mhz t plh , t phl maximum propagation delay, latch clock to q h (figures 1 and 8) 2.0 4.5 6.0 210 42 36 265 53 45 315 63 54 ns t plh , t phl maximum propagation delay , shift clock to q h (figures 2 and 8) 2.0 4.5 6.0 175 35 30 220 44 37 265 53 45 ns t phl maximum propagation delay , reset to q h (figures 3 and 8) 2.0 4.5 6.0 175 35 30 220 44 37 265 53 45 ns t plh , t phl maximum propagation delay, serial shift/ parallel load to q h (figures 4 and 8) 2.0 4.5 6.0 175 35 30 220 44 37 265 53 45 ns t tlh , t thl maximum output transition time, any output (figures 1 and 8) 2.0 4.5 6.0 75 15 13 95 19 16 110 22 19 ns c in maximum input capacitance - 10 10 10 pf power dissipation capacitance (per package) typical @25 c,v cc =5.0 v c pd used to determine the no-load dynamic power consumption: p d =c pd v cc 2 f+i cc v cc 50 pf
in74hc597 436 timing requirements (c l =50pf,input t r =t f =6.0 ns) v cc guaranteed limit symbol parameter v 25 c to -55 c 85 c 125 c unit t su minimum setup time, parallel data inputs a-h to latch clock (figure 5) 2.0 4.5 6.0 100 20 17 125 25 21 150 30 26 ns t su minimum setup time, serial data input s a to shift clock (figure 6) 2.0 4.5 6.0 100 20 17 125 25 21 150 30 26 ns t su minimum setup time, serial shift/parallel load to shift clock (figure 7) 2.0 4.5 6.0 100 20 17 125 25 21 150 30 26 ns t h minimum hold time, latch clock to parallel data inputs a-h (figure 5) 2.0 4.5 6.0 25 5 5 30 6 6 40 8 7 ns t h minimum hold time, shift clock to serial data input s a (figure 6) 2.0 4.5 6.0 5 5 5 5 5 5 5 5 5 ns t rec minimum recovery time, reset inactive to shift clock (figure 3) 2.0 4.5 6.0 100 20 17 125 25 21 150 30 26 ns t w minimum pulse width, latch clock and shift clock (figures 1 and 2) 2.0 4.5 6.0 80 16 14 100 20 17 120 24 20 ns t w minimum pulse width, reset (figure 3) 2.0 4.5 6.0 80 16 14 100 20 17 120 24 20 ns t w minimum pulse width, serial shift/parallel load (figure 4) 2.0 4.5 6.0 80 16 14 100 20 17 120 24 20 ns t r , t f maximum input rise and fall times (figure 1) 2.0 4.5 6.0 1000 500 400 1000 500 400 1000 500 400 ns
in74hc597 437 function table inputs resulting function operation reset serial shift/ parallel load latch clock shift clock serial input s a parallel inputs a-h latch contents shift register contents output q h reset shift register l x l,h, x x x u l l reset shift register; load parallel data into data latch lx xxa-ha-h l l load parallel data into data latch hh l,h,xa-ha-h u u transfer latch contents to shift register h l l,h, x x x u lr n sr n lr h contents of data latch and shift register are unchanged h h l,h, l,h, x x u u u load parallel data into data latch and shift register h l x x a-h a-h a-h h shift serial data into shift register hh x dx *sr a =d; sr n sr n+1 sr g sr h load parallel data into data latch and shift serial data into shift register hh da-ha-hsr a =d; sr n sr n+1 sr g sr h sr = shift register contents x = don?t care lr = latch register contents a-h = data at parallel data inputs a-h d = data (l,h) at serial data input s a * = depends on latch clock input u = remains unchanged inputs: a, b, c, d, e, f, g, h - parallel data inputs. data on these inputs is stored in the input latch on the rising edge of the latch clock input. s a - serial data input. data on this input is shifted into the shift register on the rising edge of the shift clock input if serial shift/parallel load is high. data on this input is ignored when serial shift/ parallel load is low. serial shift/parallel load - shift register mode control. when a high level is applied to this pin, the shift register is allowed to serially shift data. when a low level is applied to this pin, the shift register accepts parallel data from the input latch, and serial shifting is inhibited. reset - asynchronous, active-low shift register reset. a low level applied to this input resets the shift register to a low level, but does not change the data in the input latch. shift clock - serial shift register clock. a low- to-high transition on this input shifts data on the serial data input into the shift register and data in stage h is shifted out q h , being replaced by the data previously stored in stage g. latch clock - a low-to-high transition on this input loads the parallel data on inputs a-h into the input latch. output: q h - serial data output. this pin is the output from the last stage of the shift register.
in74hc597 438 figure 1. (serial shift/parallel load = l) figure 2. (serial shift/parallel load = h) figure 3. switching waveforms figure 4. switching waveforms figure 5. switching waveforms figure 6. switching waveforms figure 7. test circuit figure 8. test circuit
in74hc597 439 timing diagram
in74hc597 440 expanded logic diagram
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